Japanese application, Ser. No. 54-92061 published Feb. 17, 1981, describes an ADC comprising a bipolar transistor in combination with CMOS field effect transistors (FET) to provide high performance and low power consumption. More specifically, the output from a bipolar comparator is supplied by way of a single static latch and a two-input AND gate to the CMOS FET. This ADC does not address or improve soft error rate or metastability or provide protection against errors due to noise or propagation delays.